1. Field of the Invention
The present invention relates to a memory testing method and a memory testing apparatus for testing a memory having block function called, for example, a flash memory that the stored data therein can be electrically erased in all bits en bloc or in block by block en bloc and new data can be rewritten therein.
2. Description of the Related Art
Among PROMs (programmable read only memories) which are rewritable read only memories is called “flash memory” in this technical field a memory the stored contents of which are replaceable by electrically erasing the stored contents in all bits en bloc or in block by block en bloc and rewriting data therein. As shown in FIG. 4, such flash memory has its internal structure separated into a plurality of blocks (in this example, 1024 blocks from block No. 1 to block No. 1024). Each of the blocks is constituted by N pages (N is an integer equal to or greater than 2), and each of the N pages is constituted by M bits (M is an integer equal to or greater than 2). The flash memory has block function by which the stored contents thereof can be electrically erased not only in all bits en bloc but also in block by block en bloc, and therefore, the stored contents thereof can be replaced by rewriting new data in one or more blocks or in all blocks from which the stored contents have been erased. In general, there are many cases that each block comprises 16 pages (N=16) and each page comprises 512 bits (M=512) to 2048 bits (M=2048).
Conventionally, such flash memory is tested and measured by a memory testing apparatus adapted for testing and measuring commonplace memories (for example, IC memories constituted by semiconductor integrated circuits). FIG. 5 shows, in block diagram, a general construction of the typical memory testing apparatus that has been heretofore used.
The illustrated memory testing apparatus comprises a main controller 100, a testing apparatus proper 200 called “main frame” in this technical field (the testing apparatus proper 200 being referred to as main frame, hereinafter) and a test head 300 separately constructed from the main frame 200. The main frame 200 comprises, in this example, a timing generator TG, a pattern generator PG, a waveform formatter FC, drivers DR, a voltage comparator VCP, a logical comparator LOC, and a failure analysis memory AFM.
The test head 300 constructed separately from the main frame 200 usually has a predetermined number of device sockets (not shown) mounted on the top portion of the test head 300. In addition, printed boards each called “pin card” in this technical field are accommodated within the test head 300, and each pin card usually has a circuit containing one driver DR and one voltage comparator VCP of the main frame 200 formed thereon.
In general, the test head 300 is mounted to a test section of a semiconductor device transporting and handling apparatus called “handler” in this technical field, and the test head 300 is electrically connected to the main frame 200 by signal transmission means such as cables, optical fibers or the like.
A memory to be tested (a memory under test) MUT is mounted on a device socket of the test head 300, through which a test pattern signal is written in the memory under test MUT from the main frame 200 and a response signal read out of the memory under test MUT is supplied to the main frame 200, thereby to perform the test and the measurement for the memory under test MUT.
Further, in FIG. 5 only the drivers DR are shown in the plural form (four in this example), but, in reality, there are provided a predetermined number (which is, for example equal to the number of input/output pins of the memory under test MUT) of drivers DR (if the number of input/output pins of the memory under test MUT is, for example, 512, then 512 drivers DR are provided). In addition, in FIG. 5, in order to simplify the drawing, each of the components in the main frame 200 except the drivers DR (the timing generator TG, the pattern generator PG, the waveform formatter FC, the voltage comparator VCP, and the logical comparator LOC) is shown as one block, but in practice the remaining components in the main frame 200 except the timing generator TG and the failure analysis memory AFM are also provided by the same number (for example, 512) as that of the drivers DR, respectively. It is needless to say that the construction of the main frame is not limited to such construction as mentioned above.
The main controller 100 is constituted by a computer system having its scale of, for example, a workstation or so, and a test program 101 created by a user (programmer) is previously stored therein, and it controls the entire memory testing apparatus in accordance with the test program 101. The main controller 100 is connected to the timing generator TG, the pattern generator PG, and the like in the main frame 200 via a tester bus 201, and transfers test conditions described in the test program 101 to the pattern generator PG and the timing generator TG to initialize them. The main controller 100 controls the pattern generator PG and the timing generator TG in accordance with the initialized conditions to carry out a testing for the memory under test MUT.
When a control instruction or command is given to the pattern generator PG from the main controller 100, the pattern generator PG outputs test pattern data to be applied to the memory under test MUT in accordance with the initialized condition (for example, pattern generating sequence) stored therein.
The timing generator TG outputs, when a control instruction or command is given thereto from the main controller 100, various kinds of timing clocks (timing pulses) for each test period in accordance with the initialized condition (for example, various kinds of timing data outputted for every test period) stored therein.
The waveform formatter FC defines a rise timing and a fall timing of a signal waveform on the basis of the test pattern data outputted from the pattern generator PG and the timing pulses outputted from the timing generator TG, to produce a test pattern signal having a real waveform that changes from/to logical H (logical “1”) to/from logical L (logical “0”).
Each of the drivers DR defines the amplitude of the test pattern signal outputted from the waveform formatter FC to a desired amplitude (logical H, i.e., voltage of logical “1” or logical L, i.e., voltage of logical “0”) and applies such test pattern signal to the device socket of the test head 300, thereby to drive the memory under test MUT.
The voltage comparator VCP determines whether a logical value of a response signal outputted from the memory under test MUT has a normal voltage value or not. That is, the voltage comparator VCP determines whether or not a voltage of logical H has a value equal to or greater than the defined voltage value in case the response signal is of logical H and whether or not a voltage of logical L has a value equal to or less than the defined voltage value in case the response signal is of logical L.
In case the determination result of the voltage comparator VCP indicates a good result (pass), the output signal of the voltage comparator VCP is inputted to the logical comparator LOC where it is compared with an expected value pattern data (signal) EXP supplied from the pattern generator PG, thereby to determine whether or not the memory under test MUT has outputted a normal response signal. The comparison result of the logical comparator LOC is stored in the failure analysis memory AFM.
When the output signal of the voltage comparator VCP does not coincide with the expected value pattern data, the logical comparator LOC determines a memory cell of the memory under test MUT at the address thereof from which the response signal has been read out to be defective or failure, and generates a failure signal indicating that fact. Usually, when the failure signal is generated, a logical “1” signal being always applied to a data input terminal of the failure analysis memory AFM is enabled to be written in the failure analysis memory AFM, and the logical “1” data is written as a failure data in a memory cell of the failure analysis memory AFM specified by an address signal ADR supplied from the pattern generator PG. In general, a failure data (logical value “1”) is stored in the same address of the failure analysis memory AFM as that of the failure memory cell of the memory under test MUT.
On the contrary, when the response signal from the memory under test coincides with the expected value pattern data EXP, the logical comparator LOC determines a memory cell of the memory under test MUT at the address thereof from which the response signal has been read out to be normal, and generates a pass signal indicating that fact. Usually, the pass signal is not stored in the failure analysis memory AFM.
After the test has been completed, a failure analysis of the memory under test MUT is carried out with reference to the failure data stored in the failure analysis memory AFM. For example, in case the failure data are utilized for repair or relief of the failure memory cells, a failure map will be created based on the read-out failure data whereby a decision will be rendered as to whether the repair or relief of the failure memory cells of the memory under test MUT can be carried out or not.
As is well known, the failure analysis memory AFM is constructed by a memory having its storage capacity equal to or more than that of the memory under test MUT so that the data representing the failure/pass determination results of all the bits of the memory under test MUT can be stored therein.
Accordingly, even in case of testing a flash memory, heretofore, the data representing the failure/pass determination results of all the bits of the flash memory are also stored in the failure analysis memory AFM. After the test has been completed, the stored data are utilized, for example, in case of carrying out a failure repair analysis in which a decision is rendered whether the repair of the failure memory cells is possible or not by supplying an address signal to the failure analysis memory AFM to discriminate each of the blocks of the flash memory, and then counting the number of failure memory cells for each block.
FIG. 6 is a structural diagram for explaining a failure repair structure of the semiconductor chip forming a general flash memory. In the semiconductor chip CHP are provided a first and a second two memory forming sections A1 and A2 for forming a flash memory therein, a first and a second two spare column cell line forming sections B1 and B2 for forming therein a spare memory cell line or lines in the column direction (up-and-down direction on the figure, which is the same direction as that of the row address direction) respectively, and a first and a second two spare block forming sections C1 and C2 for forming a spare block or blocks therein respectively. Here, “cell line” is equivalent to “memory cell line” and means a series of memory cells arranged in a line in the row direction (up-and-down direction) or in the column direction (left and right direction).
In the illustrated example, block No. 1 to block No. 512 of the flash memory are formed in the first memory forming section A1 and block No. 513 to block No. 1024 of the flash memory are formed in the second memory forming section A2. Further, there is shown in FIG. 6 a case that the two memory forming sections A1 and A2 are provided in the semiconductor chip CHP. However, this case is merely one example of the failure repair structure of the semiconductor chip forming a general flash memory, and hence the number of the memory forming sections provided in the semiconductor chip CHP can be arbitrarily selected. The number of the spare column cell line forming sections and the number of the spare block forming sections will be increased or decreased in correspondence to increase or decrease of the number of the memory forming sections.
In the first spare column cell line forming section B1 are formed a predetermined number of spare column cell lines SC for repairing one or more failure memory cells on the column address lines in the first memory forming section A1. In this example, a case is shown that four spare column cell lines SC are formed in the first spare column cell line forming section B1. In the second spare column cell line forming section B2 are formed a predetermined number of spare column cell lines SC for repairing one or more failure memory cells on the column address lines in the second memory forming section A2. These spare column cell lines SC are provided for substituting oneself, in case that one or more failure memory cells have been detected on at least one specified column address line formed in the corresponding first or second memory forming section A1 or A2, for the memory cell line or lines including such failure memory cell or cells on the specified column address line or lines. By this substitution, the memory cell line or lines including at least one failure memory cell on the specified column address line or lines are repaired or relieved, the flash memory including one or more failure memory cells, that is, the defective flash memory can be changed to a good or pass article.
In the first and second spare block forming sections C1 and C2 are formed respectively a plurality of (four in this example) spare blocks SB. The plurality of spare blocks SB are provided for substituting oneself, in case that one or more failure blocks have been detected in the corresponding first or second memory forming section A1 or A2, for such failure block or blocks. By this substitution, the failure block or blocks can be repaired or relieved, the flash memory including one or more failure blocks, that is, the defective flash memory can be changed to a good or pass article.
A test for a flash memory is performed on the basis of one block by one block. For example, the block No. 1 which is the first block of the flash memory is accessed by the corresponding row address, and then the memory cells in the accessed block No. 1 are sequentially accessed in the column address direction (left and right direction on the figure) from the address 1 thereof until the last address thereof, thereby to write a predetermined logical value (a test pattern signal) in each memory cell. Thereafter, the written logical values are read out therefrom and are compared with an expected value. For example, in case a flash memory to be tested is a NAND type one, the detection of failure memory cell thereof is effected by writing a logical value “0” in all of the memory cells of the flash memory under test, reading out the logical value “0” therefrom, comparing the read-out logical value “0” with an expected value (its logical value is “0”), and determining whether the logical value “0” has been correctly written in each memory cell or not. The NAND type flash memory has its property that it outputs a logical value “1” in the unwritten state in which any data (any logical value) is not written in all of the memory cells thereof. Therefore, a test for a flash memory has to carry out by writing a logical value “0” in all of the memory cells of the flash memory under test. Writing a logical value “0” in and reading out the logical value “0” from each of the memory cells of the flash memory under test are performed on the basis of, for example, 6 bits by 6 bits at the same time.
As discussed above, the prior memory testing apparatus uses the failure analysis memory AFM having its storage capacity equal to or more than that of the memory under test MUT and the same address structure as that of the memory under test MUT, and stores the addresses of the failure memory cells for each of the blocks of the memory under test MUT in the failure analysis memory AFM. After the test has been completed, the testing apparatus supplies an address signal ADR to the failure analysis memory AFM to discriminate each block of the flash memory, and then counts the number of failure memory cells for each block. Thereafter, a decision is rendered whether the repair of the failure memory cells is possible or not within the number of the spare column cell lines SC and the number of the spare blocks SB. Consequently, there is a drawback that the time duration required for carrying out the failure repair analysis becomes considerably long.
Moreover, since the flash memory is a non-volatile memory, there may be a case due to its characteristic in which a failure memory cell or cells that at first data cannot be written therein and cannot be read out therefrom will change to normal memory cell or cells that data can be written therein and can be read out therefrom during a writing operation and a reading operation are being repeated several times for such failure memory cell or cells. For this reason, in the inside of the flash memory are added a function that decides whether writing of data in a memory cell is correctly performed or not as well as a function that unless writing of data in a memory cell is correctly performed, performs rewriting of data in a memory cell. Though the number of rewriting operations is limited to six times or so at the maximum, in case of a failure memory cell that data cannot be written therein, the rewriting operation is repeated until the number of the rewriting operations reaches a preset number of times. When the number of the rewriting operations reaches a preset number of times, the writing of data in the current address is ceased and the writing operation proceeds to the next address. At the same time, the address in which the writing of data could not have been done is stored in the failure analysis memory AFM as a failure address. Accordingly, there is a drawback that the time duration required for carrying out the rewriting operations becomes considerably long. As a result, there is an important defect that the time duration required for testing a flash memory becomes long in proportion to the number of failure memory cells.
In addition, in case a plurality of flash memories are simultaneously tested, even if there exists only one flash memory having its block containing a failure address, the writing operation for this flash memory is repeated a predetermined number of times when the failure address thereof is accessed. As a result, the remaining flash memories must await until the writing operation for the failure address is repetitively carried out predetermined number of times, notwithstanding that the writing operation for each of the remaining flash memories has been completed only once. Accordingly, there is a serious drawback that the remaining flash memories spend a waste of time, which results in longer test time.
In recent years, in order to reduce a testing cost, many semiconductor memory testing apparatus each being able to test and measure a multiplicity of (for example, 64) semiconductor memories at the same time have appeared, and when many flash memories are simultaneously tested by such a semiconductor memory testing apparatus, there is a strong possibility that at least one flash memory among them has its block including a failure address. Accordingly, the aforesaid drawback resulting in longer test time eventually brings about an increase of the testing cost.